October 2021 - December 2021
Collaborating with a partner, I spearheaded the development and testing of an MIPS processor using VHDL. The CPU was a 32-bit five-stage processor, designed to MIPS architecture standards while optimizing for performance and efficiency.
In addition to the hardware development, we wrote various assembly programs to test the functionality and performance of our processor. These programs ranged from complex control flow and data manipulation tasks to sorting algorithms.