MISP Architecture Design and Implementation

October 2021 - December 2021

Overview

Collaborating with a partner, I spearheaded the development and testing of an MIPS processor using VHDL. The CPU was a 32-bit five-stage processor, designed to MIPS architecture standards while optimizing for performance and efficiency.

In addition to the hardware development, we wrote various assembly programs to test the functionality and performance of our processor. These programs ranged from complex control flow and data manipulation tasks to sorting algorithms.

MIPS CPU Diagram

Skills Developed

Assembly
VHDL
Microarchitecture

Links

CPRE381_Project
GitHub Repo
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https://github.com/liama28/CPRE381_Project